1. Field of the invention
The present invention relates to an improved fabrication process for CMOS integrated devices having a reduced gate length and lightly doped drain regions of transistors of both polarities.
2. Description of the prior art
At present in CMOS fabrication processes with a gate length of about a micron (.mu.m) or less, the p-channel transistors are fabricated with dimensions greater than the minimum dimensions proper of the fabrication process because the high diffusivity of the p-type dopant commonly used for p.sup.+ junctions, typically boron, produces an effective channel length sensibly reduced in respect to the one obtained in n-channel transistors having the same gate length, when using conventional heat treatments. In this situation the p-channel transistors are much more subject to develop malfunctioning problems, such as the punch-through phenomenon, than n-channel transistors especially in devices destined to operate with a relatively high supply voltage (12 V), and therefore must necessarily be fabricated with adequately increased dimensions, thus reducing the density of integration which may be achieved. In the alternative the problem may be overcome by means of the known technique of forming lightly doped drain regions close to the sides of the transistors' gate. The use of lightly doped drain regions allows to exploit the minimum dimensions of definition of the fabrication process also for p-channel transistors, by spacing apart the p.sup.+ diffusions by means of spacers of dielectric material which are purposely formed on the sides of the gate, according to well known techniques. The formation of lightly doped drain regions commonly implies the repetition of the n.sup.+ and p.sup.+ implantations maskings in order to repeat the implantation of the relevant dopants before and after forming the spacers. This increases substantially fabrication costs because of the two additional masking operations which are required in respect to a standard process (without the formation of lightly doped drain regions, or LDD) or to a process wherein the formation of said lightly doped drain regions takes place on transistors of a single polarity.